Instruction Set
Complete reference for CIM compute, communication, and control instructions
Instruction Overview
The instruction set is designed based on the RISC philosophy, with each fundamental instruction corresponding to one of three basic operations: compute, communication, and control flow.
| Operation Type | Mnemonic | Description | Key Operands |
|---|---|---|---|
| Matrix–Vector Operation | CIM_MVM | Matrix–vector multiply-accumulate on in-memory-computing array | input-address, input-length, optional-flags, weight, batch |
| Vector Operation | VEC_OP | Single-instruction multiple-data operation | src1, src2, length, dst, functor |
REDUCE | Vector reduction/aggregation operation | src, length, dst, functor | |
| Scalar Operation (Compute) | SC_RR | Scalar data operation | rs, rt, rd, functor |
SC_RI | rs, rd, functor | ||
| Scalar Operation (Comm) | SC_LD | Scalar data load/store | rs, rd, offset |
SC_ST | rs, rt, offset | ||
G_LI | Scalar assignment | rd, imm | |
S_LI | rd, imm | ||
GS_MOV | rs, rd | ||
SG_MOV | rs, rd | ||
| Data Movement | MEM_CPY | Data copy among memory resources (local / global memory) | src, length, dst |
| Inter-Core Communication | SEND | Send data across cores | src, dst, core-id, length, tag |
RECV | Receive data across cores | src, dst, core-id, length, tag | |
| Intra-Core Control | BRANCH | Conditional branch | rs, rt, offset, cond |
JMP | Unconditional jump | offset | |
| Inter-Core Synchronization | WAIT | Wait for synchronization point from another core | src-id, sync-id, expected-writes |
BARRIER | Collective barrier synchronization | core-count, barrier-id | |
TAG | Mark synchronization point for other cores | sync-id |
Instruction Encoding
Instructions are grouped by their encoding type: R, I-A, I-B, I-C, and J.
| Type | Instruction | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:1 | 0 |
|---|---|---|---|---|---|---|---|---|
| R | CIM_MVM | 000000 | rs | rt | re | rf | flags | |
VEC_OP | 01XX00 | rs | rt | rd | re | funct | ||
REDUCE | 010001 | rs | rt | rd | 0 0000 | funct | ||
SC_RR | 100000 | rs | rt | rd | 0 0000 | funct | ||
SEND | 110100 | rs | rt | rd | re | rf | ||
RECV | 110110 | rs | rt | rd | re | rf | ||
| I-A | SC_RI | 100100 | rs | rd | funct | imm | ||
MEM_CPY | 1100XY | rs | rt | rd | imm | |||
WAIT | 111101 | rs | rt | rd | 0 0000 0000 00 | |||
| I-B | SC_LD | 101000 | rs | rd | imm | |||
SC_ST | 101001 | rs | rt | imm | ||||
GS_MOV | 101110 | rs | rd | 0000 0000 0000 0000 | ||||
SG_MOV | 101111 | rs | rd | 0000 0000 0000 0000 | ||||
BRANCH | 1110XX | rs | rt | imm | ||||
BARRIER | 111110 | rs | rt | 0000 0000 0000 0000 | ||||
| I-C | G_LI | 101100 | rd | imm | ||||
S_LI | 101101 | rd | imm | |||||
TAG | 111111 | rs | 0 0000 0000 0000 0000 0000 | |||||
| J | JMP | 111100 | imm | |||||
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