Instruction Design

CIMFlow uses a unified 32-bit instruction format with specialized encodings for different operation types: compute, communication, and control flow.

Instruction Format

All instructions are 32 bits with a 6-bit opcode. The remaining 26 bits vary by encoding type. See Instruction Set for the complete instruction list.

Each instruction contains:

Opcode (6 bits): Operation identifier
Operand fields (5 bits each): Register addresses (rs, rt, rd, re, rf)
Tail field (variable width): Function code, flags, or immediate value

Type	31:26	25:21	20:16	15:11	10:6	5:0
`R`	`opcode`	`rs`	`rt`	`rd`	`re/rf`	`tail`
`I-A`	`opcode`	`rs`	`rt/rd`	`rd/funct`	`imm`
`I-B`	`opcode`	`rs`	`rt`	`imm`
`I-C`	`opcode`	`rd`	`imm`
`J`	`opcode`	`imm`

Instruction Categories

Compute

CIM matrix ops, vector element-wise, scalar arithmetic

Communication

Inter-core data movement, memory load/store

Control Flow

Branches, loops, synchronization barriers

Register Files

General Register File (GRF)

32 registers (r0-r31) encoded with 5-bit addresses for arithmetic, address calculation, and temporary storage.

Special Register File (SRF)

32 registers split between CIM unit (IDs 0-15) for array configuration and Vector unit (IDs 16-31) for activation and reduction parameters. See Register Files for the complete register map.