Register Files
General and special register files for CIM cores
Each core maintains two register files: a General Register File (GRF) for arithmetic and addressing, and a Special Register File (SRF) for hardware configuration.
General Register File (GRF)
32 general-purpose registers (r0–r31) encoded with 5-bit addresses. Used for:
- Arithmetic operations: Counters, loop indices, intermediate values
- Address calculation: Base addresses, offsets, pointers
- Temporary storage: Function arguments, return values
Register r0 is hardwired to zero. Writes to r0 are ignored.
Special Register File (SRF)
32 special-purpose registers configure the CIM and Vector execution units.
CIM Configuration (IDs 0-15)
Bit Widths
CIM_IBWID 0Input bit width
CIM_OBWID 1Output bit width
CIM_WBWID 2Weight bit width
Array Configuration
CIM_GSZID 3Macros per group
CIM_AGID 4Active groups
CIM_AEID 5Active elements per column
CIM_GSTEPID 6Group input step offset
IDs 7-15 are reserved.
Vector Configuration (IDs 16-31)
Input Bit Widths
VEC_IBW1ID 16Input 1 bit width
VEC_IBW2ID 17Input 2 bit width
VEC_IBW3ID 18Input 3 bit width
VEC_IBW4ID 19Input 4 bit width
Output & Addresses
VEC_OBWID 20Output bit width
VEC_IA3ID 21Input 3 address
VEC_IA4ID 22Input 4 address
IDs 23-31 are reserved.
Register Binding
Special-purpose registers can be bound to general-purpose registers to reduce assignment overhead.
[
{ "special": 3, "general": 30 },
{ "special": 4, "general": 31 }
]This binds CIM_GSZ (ID 3) to r30 and CIM_AG (ID 4) to r31.
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