CIMFlow LogoCIMFlow

CIMFlow Framework

An integrated framework for digital CIM accelerator design and simulation

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CIMFlow provides an end-to-end solution for designing and evaluating SRAM-based Compute-in-Memory accelerators. The framework integrates an MLIR-based compiler with a cycle-accurate SystemC simulator, enabling researchers and engineers to explore CIM architectures from neural network models to detailed performance analysis.


Documentation


Framework Components

Compiler
MLIR-based toolchain with two-level optimization: CG-level workload partitioning and OP-level code generation
Simulator
Cycle-accurate SystemC simulator with energy tracking, memory hierarchy, and detailed profiling
CLI
Unified command-line interface for compilation, simulation, and batch processing workflows

Who Is This For?

Researchers
Explore CIM architecture design spaces and analyze performance-energy tradeoffs
Hardware Engineers
Validate accelerator designs with cycle-accurate simulation before implementation
ML Engineers
Evaluate neural network deployments on CIM hardware with realistic performance estimates

To get started, see Installation and Quickstart.


Prerequisites

Familiarity with the following is helpful:

  • CIM fundamentals: See Literatures on SRAM-based CIM for background
  • ONNX format: CIMFlow accepts neural network models in ONNX format
  • Command-line usage: Terminal navigation and shell commands

No prior experience with MLIR or SystemC is required.

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