Pipeline Overview

CIMFlow-Compiler provides a two-level compilation flow:

CG-level: partition model graph and generate stage/core tasks
OP-level: lower tasks to executable ISA sequences

A separate DSL and MLIR backend (see DSL and MLIR Backend) generates low-level ISA code for operator kernels like convolution.

Compilation Paths

cim-compiler network \
  -m model.onnx \
  -o output \
  -c config.json \
  -T 8 -K 16 -B 16 -C 64 \
  --batch-size 8 --strategy dp

Input: ONNX model + hardware config.
Output: unified ISA JSON (isa_instructions_*.json).

Stage Graph

The graph below corresponds to the full cim-compiler network path.

ONNX

Model Simplify

CG-Level

CG IR

OP-Level

ISA JSON

The Model Simplify stage performs ONNX preprocessing, including operator fusion (e.g., BatchNorm folding) and shape inference. The CG IR output (instructions_<...>.json) serves directly as OP-level input — when running the two-step process, the CG output directory becomes the OP input path.

Output Files

Typical output structure for cim-compiler network:

isa_instructions_<model>_<strategy>_T<T>_K<K>_B<B>_C<C>_batch<N>.json

instructions_<...>.json (optional, when --keep-cg-ir)

Typical output structure for staged flow:

instructions_<model>_<strategy>_T<T>_K<K>_B<B>_C<C>_batch<N>.json

isa_<cg_filename>.json (e.g., isa_instructions_<...>.json)

Pipeline Overview

Compilation Paths

Stage Graph

Output Files

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